IHP SG13G2 Process Design Kit (PDK) for Revolution EDA

A comprehensive Python-based Process Design Kit (PDK) for the IHP SG13G2 130nm BiCMOS technology integrated with the Revolution EDA open-source IC design environment.

Overview

This PDK provides complete design automation support for IHP’s SG13G2 process node, including:

  • Parametric layout cells (pcells) for automated device and passive component generation
  • Instance parameter callbacks for electrical parameter computation
  • Schematic and symbol layer definitions for front-end design
  • Layout layer definitions with GDS layer/datatype mappings
  • Design Rule Checking (DRC) integration via KLayout
  • SPICE simulation models and Verilog-A modules for transient and AC analysis

Technology Details:

  • Process Node: SG13G2 (IHP 130nm BiCMOS)
  • PDK Version: 0.2.0
  • License: Apache 2.0

What’s Implemented

1. Parametric Cells (PCell Library)

The PDK includes 6 parametric layout cells enabling automated, scalable device generation:

Active Devices

CellDescriptionParameters
nmosNMOS transistor with configurable fingerswidth, length, ng (number of gates)
pmosPMOS transistor with configurable fingerswidth, length, ng (number of gates)
rfnmosRF-optimized NMOS with guard ringswidth, length, ng, cnt_rows, Met2Cont, gat_ring, guard_ring
rfpmosRF-optimized PMOS with guard ringswidth, length, ng, cnt_rows, Met2Cont, gat_ring, guard_ring

Passive Components

CellDescriptionParameters
rsilPolysilicon resistor (meander pattern)length, width, b (bends), ps (poly spacing)
cmimMetal-insulator-metal capacitorw, l, mf (multiplier factor)

Key Features:

  • All pcells support parameterized layout generation at instantiation time
  • Automatic contact array placement with correct spacing and alignment
  • Technology-aware grid snapping and design rule compliance
  • Support for multi-finger and multi-unit configurations
  • RF variants include guard rings and shielding for low-noise applications

2. Instance Callbacks

The callbacks.py module provides automatic electrical parameter computation for 50+ device variants:

Capacitor Classes:

  • cap_cmim - Metal-insulator-metal capacitor with calculated capacitance
  • cap_cpara - Parameterized capacitor
  • cap_rfcmim - RF-optimized MIM capacitor

MOSFETs:

  • NMOS/PMOS variants (low-voltage, high-voltage, thick-oxide gate)
  • Multiple drive strengths

Passive Devices:

  • Resistors (silicon, polysilicon, high-resistance)
  • Diodes (various junction types and configurations)

Other Devices:

  • HBT (Heterojunction Bipolar Transistor) models
  • ESD protection structures
  • Bond pads and antenna structures

Example: When you instantiate a cap_cmim device with width and length parameters, the callback automatically calculates its capacitance using the formula:

C = MF × (W × L × 1.5e-3 + 2 × (W + L) × 40e-12)

3. Layer Definitions

Schematic/Symbol Layers (schLayers.py)

The PDK defines comprehensive schematic drawing layers:

  • Wire layers: Standard signal wires, error indication, selection highlighting
  • Bus layers: Multi-signal buses with distinctive appearance
  • Component layers: Pin labels, port connections, annotation text
  • Structural layers: Symbolic representation of devices (rectangles, circles, polygons)

Each layer is a PySide6 Qt graphics-enabled dataclass with configurable:

  • Colors, line styles, line widths
  • Fill patterns and brush styles
  • Z-order (rendering depth)
  • Visibility and selectability toggles

Layout Layers (layoutLayers.py)

Complete layout layer set for GDS II file I/O:

Metallization Layers:

  • Metal1–Metal4 (drawing + pin layers)
  • Via1–Via4 (contact/via layers)
  • Contact layers (Cont_drawing)

Active Device Layers:

  • Active region (Activ_drawing)
  • N-well, P-well (NWell_drawing, pBuLay_drawing)
  • Gate poly (GatPoly_drawing, GatPoly_pin)

Mask Definition Layers:

  • Thick gate oxide (ThickGateOx_drawing)
  • Implant layers (pSD_drawing, nBuLay_drawing)
  • High-voltage layers for 3.3V/6V devices

Special Layers:

  • Polysilicon resistor mask (PolyRes_drawing)
  • MIM capacitor (MIM_drawing, Vmim_drawing)
  • Externally defined blocks (EXTBlock_drawing)
  • Heat transfer annotation (HeatTrans_drawing)

Each layout layer is mapped to specific GDS layer/datatype pairs per IHP specifications.

4. Design Rule Checking (DRC)

KLayout DRC Integration:

  • Headless KLayout DRC execution with IHP rule decks
  • DRC result parsing and error visualization in Revolution EDA
  • Menu integration: Check → DRC with KLayout (Ctrl+Shift+D)

Included Rule Files:

  • sg13g2_maximal.lydrc - Full rule checking (all design rules)
  • sg13g2_minimal.lydrc - Essential rules only (faster runs)

DRC violations are parsed and displayed as a table with:

  • Error classification (layer/rule pair)
  • Error location coordinates
  • Interactive error highlighting on layout

5. SPICE Simulation Models

Complete model library for analog circuit design:

Compact Models (.lib files):

  • sg13g2_moslv_stat.lib - Low-voltage MOSFET models (statistical)
  • sg13g2_moshv_stat.lib - High-voltage MOSFET models (statistical)
  • sg13g2_hbt_stat.lib - HBT transistor models
  • Device-specific models: capacitors, diodes, resistors, ESD structures

Parametric Models:

  • Temperature variation (*_mod.lib)
  • Process corners (corner*.lib)

Verilog-A Modules:

  • PSP103 MOSFET model (libXyce_Plugin_PSP103_VA.so)
  • Enables advanced RF/analog simulation with Xyce

6. Process Technology Parameters

The sg13_tech.py and process.py modules define:

  • Distance unit (DBU): 1 nm precision
  • Snap grid: 50 nm
  • Major grid: 100 nm
  • GDS unit: 1 nm with 1 nm precision

Via Definitions:

  • Via types: Contact (cont), Via1–Via4, MIM via, barrier contact (contBar)
  • Each via has min/max width, height, and spacing constraints
  • Example: cont via is 0.16 µm square with 0.18 µm minimum spacing