IHP SG13G2 Process Design Kit (PDK) for Revolution EDA

A comprehensive Python-based Process Design Kit (PDK) for the IHP SG13G2 130nm BiCMOS technology integrated with the Revolution EDA open-source IC design environment.

Overview

This PDK provides complete design automation support for IHP’s SG13G2 process node, including:

  • Parametric layout cells (pcells) for automated device and passive component generation
  • A complete device library (sg13g2_pr) pairing schematic symbols with pcell layout views
  • Instance parameter callbacks for electrical parameter computation
  • Schematic and symbol layer definitions for front-end design
  • Layout layer definitions with GDS layer/datatype mappings
  • Design Rule Checking (DRC) and Layout vs. Schematic (LVS) integration via KLayout
  • RC parasitic extraction (PEX) with process-corner technology data
  • Xyce and VACASK simulation models, including compiled Verilog-A/OSDI modules

Technology Details:

  • Process Node: SG13G2 (IHP 130nm SiGe BiCMOS)
  • PDK Version: 0.2.0
  • License: Apache 2.0

What’s Implemented

1. Parametric Cells (PCell Library)

The PDK ports the complete IHP KLayout pcell set to Revolution EDA — 42 registered pcells covering every device family:

MOSFETs

Cell Description Parameters
nmos / pmos Standard MOSFETs with configurable fingers width, length, ng (number of gates)
nmosHV / pmosHV High-voltage MOSFETs with ThickGateOx width, length, ng
rfnmos / rfpmos RF MOSFETs with guard/gate ring options width, length, ng, cnt_rows, Met2Cont, gat_ring, guard_ring
rfnmosHV / rfpmosHV RF high-voltage MOSFETs same as RF variants plus ThickGateOx

Passive Components

Cell Description Parameters
rsil Silicide polysilicon resistor (meander pattern) length, width, b (bends), ps (poly spacing)
rhigh High-ohmic resistor (SalBlock + implants) length, width, b, ps
rppd P-poly diffusion resistor length, width, b, ps
cmim Metal-insulator-metal capacitor w, l, mf (multiplier factor)
rfcmim RF MIM capacitor with ground ring and feed lines geometry + ring options
SVaricap HV S-parameter varicap (gate-controlled) w, l, array parameters
inductor2 / inductor3 Spiral inductors (two- and three-terminal) DMIN, NR (turns), geometry

Bipolar, Diodes, and ESD

Cell Description
npn13G2 / npn13G2V / npn13G2L NPN HBTs (standard, high-voltage, low-noise) with 1–10 emitter fingers
pnpMPA Lateral PNP transistor (concentric ring structure)
dantenna / dpantenna N-type and P-type ESD protection diodes
schottky N+/Metal Schottky diode with guard rings and thermal vias
esd, diodevdd/vss_2kv, diodevdd/vss_4kv, nmoscl_2, nmoscl_4 ESD protection device family

Taps, Rings, and Utilities

Cell Description
ntap1 / ptap1 N-well and P+ substrate tap contacts
subtap / nwtap / psubtap / nwelltap Connectivity and minimum-width tap lines
guardRing Parametric multi-part guard ring (p+ substrate or n+ n-well)
via_stack Configurable multi-layer via stack
bondpad / sealring / isolbox Bond pad, chip seal ring, deep-trench isolation box
NoFillerStack DRC filler exclusion marker (per-layer nofill rectangles)

Key Features:

  • All pcells generate layout at instantiation time with technology-aware grid snapping
  • Automatic contact array placement with correct spacing and alignment
  • Multi-finger and multi-unit device configurations
  • RF variants include guard rings, gate rings, and shielding for low-noise applications
  • 100% coverage of the IHP KLayout pcell reference set (see pcells/PORTING_STATUS.md)

2. Device Symbol Library

The sg13g2_pr library ships 45 device cells — schematic symbols with matching pcell layout views for most devices — covering LV/HV/RF MOSFETs, BJTs (including five-terminal variants), resistors, capacitors, inductors, diodes, ESD devices, substrate taps, and bond pads.

3. Instance Callbacks

The callbacks.py module provides automatic electrical parameter computation for 45 device classes:

Capacitor Classes:

  • cap_cmim - Metal-insulator-metal capacitor with calculated capacitance
  • cap_cpara - Parameterized capacitor
  • cap_rfcmim - RF-optimized MIM capacitor

MOSFETs:

  • NMOS/PMOS variants (low-voltage, high-voltage, thick-oxide gate)
  • Multiple drive strengths

Passive Devices:

  • Resistors (silicon, polysilicon, high-resistance)
  • Diodes (various junction types and configurations)

Other Devices:

  • HBT (Heterojunction Bipolar Transistor) models
  • ESD protection structures
  • Bond pads and antenna structures

Example: When you instantiate a cap_cmim device with width and length parameters, the callback automatically calculates its capacitance using the formula:

C = MF × (W × L × 1.5e-3 + 2 × (W + L) × 40e-12)

4. Layer Definitions

Schematic/Symbol Layers (schLayers.py / symLayers.py)

The PDK defines comprehensive schematic drawing layers:

  • Wire layers: Standard signal wires, error indication, selection highlighting
  • Bus layers: Multi-signal buses with distinctive appearance
  • Component layers: Pin labels, port connections, annotation text
  • Structural layers: Symbolic representation of devices (rectangles, circles, polygons)

Each layer is a PySide6 Qt graphics-enabled dataclass with configurable:

  • Colors, line styles, line widths
  • Fill patterns and brush styles
  • Z-order (rendering depth)
  • Visibility and selectability toggles

Layout Layers (layoutLayers.py)

Complete layout layer set for GDS II file I/O covering the full SG13G2 stack:

Metallization Layers:

  • Metal1–Metal5 (drawing + pin layers)
  • TopMetal1–TopMetal2 thick top metals
  • Via1–Via4, TopVia1–TopVia2, and contact layers

Active Device Layers:

  • Active region (Activ_drawing)
  • N-well, P-well (NWell_drawing, pBuLay_drawing)
  • Gate poly (GatPoly_drawing, GatPoly_pin)

Mask Definition Layers:

  • Thick gate oxide (ThickGateOx_drawing)
  • Implant layers (pSD_drawing, nBuLay_drawing)
  • High-voltage layers for 3.3V/6V devices

Special Layers:

  • Polysilicon resistor mask (PolyRes_drawing)
  • MIM capacitor (MIM_drawing, Vmim_drawing)
  • Externally defined blocks (EXTBlock_drawing)
  • Heat transfer annotation (HeatTrans_drawing)

Each layout layer is mapped to specific GDS layer/datatype pairs per IHP specifications.

5. Design Rule Checking (DRC)

KLayout DRC Integration:

  • Headless KLayout execution against the SG13G2 rule decks in drc/rule_decks/
  • Full deck suite: sg13g2_maximal.drc plus FEOL, BEOL, geometry, pin, density, antenna, and forbidden-layer rule tables
  • Menu integration: Check → DRC with KLayout... (Ctrl+Shift+D)
  • Flat or deep run modes, per-table selection, and optional density/antenna subsets
  • Rule categories: verified PreCheck set, full Main rule set, and an optional unverified Extra set

DRC violations are parsed and displayed as a table with:

  • Error classification (layer/rule pair)
  • Error location coordinates
  • Interactive error highlighting on layout

6. Layout vs. Schematic (LVS)

KLayout LVS Integration:

  • Menu integration: Check → LVS with KLayout... (Ctrl+Shift+L)
  • Full extraction and comparison decks in lvs/rule_decks/: MOS, RF MOS, BJT, resistor, capacitor, diode, ESD, inductor, and tap extraction/derivation/connection decks, plus custom device extractors
  • Flat or deep hierarchical run modes
  • Series/parallel resistor combination and device merging controls
  • Netlist-only extraction and schematic-vs-schematic (SVS) comparison flows
  • Implicit-net support for bottom-up block-level verification
  • Results surface in Revolution EDA’s LVS mismatch tables, with the extracted .cir netlist and .lvsdb database available for inspection

7. RC Parasitic Extraction (PEX)

RC extraction integration:

  • Menu integration: Check → RC Extraction (PEX)... (Ctrl+Shift+X)
  • Runs on a successful LVS “Export for PEX” pass
  • Uses the pex/ihp_sg13g2.json technology file derived from the IHP extract deck
  • Per-layer sheet resistance, via resistance per cut, and area/fringe/sidewall capacitance across process corners (nominal, minimum, maximum)
  • RC and C-only extraction modes for fast parasitic views

8. Layout Creation Tools

PDK-specific menu commands wired through config.json:

  • Create → Guard Ring → Substrate Tap (p+)... / N-Well Tap (n+)... — parametric guard-ring placement
  • Create → Substrate Tap → P+ Tap Line / N-Well Tap Line — minimum-width tap lines

9. Simulation Models

Model libraries ship preconfigured through modelLibSettings.json (using ${PDK_ROOT}-relative paths) for Xyce and VACASK:

Xyce (models/xyce/):

  • Statistical and corner .lib decks for LV/HV MOSFETs, HBTs, resistors, capacitors, diodes, ESD devices, and bond pads
  • Compiled Verilog-A modules (PSP103, mosvar) for advanced RF/analog simulation

VACASK (models/vacask/):

  • Matching corner/statistical model set (MOS LV/HV, HBT, RES, CAP, DIO)
  • Precompiled OSDI modules for Linux and Windows
  • Verilog-A sources for PSP103, R3_CMC, and MOSVAR

10. Process Technology Parameters

The sg13_tech.py and process.py modules define:

  • Distance unit (DBU): 1 nm precision
  • Snap grid: 50 nm
  • Major grid: 100 nm
  • GDS unit: 1 nm with 1 nm precision

Via Definitions (9 types):

  • cont, contBar (barrier contact), viamim, via1–via4, topVia1–topVia2
  • Each via defines min/max width, height, spacing, and bottom/top layer enclosures
  • Example: cont via is 0.16 µm square with 0.28 µm minimum spacing

Path Definitions (9 types):

  • nwell, gatPoly, metal1–metal5, topMetal1–topMetal2
  • Per-layer width, spacing, and enclosure defaults for wiring

Distribution

The PDK is published through the Revolution EDA PDK registry (pdks.json) in two forms:

  • Source package — ihp_pdk-source.zip
  • Precompiled binary packages — Windows and Linux builds for Python 3.12/3.13, with faster load times